1. Field of the Invention
The invention relates to damascene processing in a semiconductor device, and more particularly, to reducing wire erosion during damascene processing.
2. Background Description
Interconnects of a semiconductor device are formed by various methods, including a damascene process. It should also be noted that the damascene process can be incorporated into the fabrication of many types of semiconductor devices such as MOSFET or bipolar junction transistors (BJT), etc., and various structures such as resistors, wires, and vias, etc. The damascene process typically includes first forming a trench in a substrate. The trench in the substrate is formed having a width which substantially corresponds to the desired final width of the interconnect. Additionally, the trench traditionally will have a depth which is slightly deeper than the desired final height or thickness of the interconnect. It should be noted that the damascene process can be used to form a variety of structures in addition to a trench, such as vias, however, all such structure will be referred to simply as trenches for simplicity.
Once the trench has been formed, the trench and adjacent surface areas of the substrate are coated with conducting material. In some damascene processes, the trench may receive a liner material which includes a thin layer of a material which is conformably deposited to the bottom and sides of the trench and the surrounding substrate surface. Additionally, some damascene processes include a metal seeding process, where a seed of trench-fill material is deposited within the trench and on the substrate surfaces to aid in bulk material deposition. For example, where the trench-fill material will be copper, a copper seed is deposited in the trench. It should be noted that the trench may be filled with a conductor or a dielectric; however, since the trench-fill in a damascene process is typically a conductor, the terms “trench-fill” and “bulk conductor” will be used synonymously herein, even though the trench-fill may also be a dielectric.
One of the potential problems of forming an interconnect or via with the damascene process is the form action at unwanted voids or inclusions in the bulk conductor as it is deposited within the trench. Accordingly, the seed deposition may help to reduce void or inclusion formation by aiding in the uniform deposition of trench-fill material. Additionally, a trench having a high aspect ratio, i.e., one that is much taller than wider will have a greater tendency to have voids or inclusions formed in the material deposited therein. Where the trench forms a wire or interconnect, voids or inclusions in the conductor of the wire or interconnect will increase the resistance of the wire or interconnect and negatively impact device performance.
After the trench-fill material has been deposited, the upper portions of the bulk conductor are removed, typically by a chemical, mechanical polishing (CMP) process. The upper portions of the bulk conductor are typically removed so that the only bulk conductor remaining lies within the trench. Thus, all or substantially all of the bulk conductor is removed from the surfaces surround the trench.
Where a liner is deposited on the substrate, the bulk conductor typically is removed from the substrate surface but substantially not from inside the trench to expose substantially all of the liner in a first polishing step. After the bulk conductor has been removed from surfaces of the substrate, any exposed portions of a liner are removed in a second polishing step. The exposed portions of the liner are usually removed by a CMP process. In certain damascene processes, the liner is a conductor, and thus it important for all of the liner material to be removed from the surfaces of the substrate surrounding the trench to prevent shorts between wires and interconnects.
Also, the surfaces of substrate underlying the liner may have topographic imperfections, such as bumps, scratches or depressions, which the liner has filled in. Accordingly, portions of the substrate which protrude above the lowest portion of the lower surface of the liner will be removed first during liner removal. Thus, for all of the liner material to be removed from any low spots on the substrate surface, a significant portion of the substrate itself may have to be removed. Additionally, the CMP process may not be uniform across the surface of the substrate, and thus, some regions of the substrate will be exposed before all of the liner has been removed, thus also necessitating removal of significant portions of the substrate in certain regions of wafer.
Because the bulk conductor has had the upper portions removed down to the top edge of the trench, any removal of the substrate will necessarily also remove portions of the bulk conductor residing in the trench. Accordingly, such unwanted removal of the bulk conductor will increase the resistivity of the interconnect. Because interconnects having higher resistivities are undesirable, the typical damascene process starts with forming a trench which is deeper than the final desired interconnect thickness. Such extra interconnect thickness remaining after the removal of the upper portions of bulk conductor allows for interconnect erosion during the final stages of liner removal. However, as noted above, because trenches with higher aspect ratios have a greater chance of void or inclusions being formed within the interconnect, increasing the depth of a trench to accommodate interconnect erosion is undesirable. Accordingly, a method for removing materials during a damascene process which avoids interconnect erosion is desirable.
As such, damascene processes typically utilize a two step metallization process in which the trenches and/or vias are filled with a thin liner follower by a thicker layer of bulk conductor. For example, for copper wiring, the liners are typically tantalum (Ta) or tantalum based material. After damascene trench formation, the process continues with a Ta liner deposition and copper deposition. The copper deposition step typically includes a plasma vapor deposition (PVD) copper seed followed by an electroplated copper layer. An anneal process may be optionally included after the bulk copper deposition.
After the bulk copper has been deposited, an upper portion of the bulk copper is removed with a copper CMP process to the exposed portions of the liner. Next, a tantalum CMP process is used to remove all of the liner on the wafer surface adjacent to the interconnects. Accordingly, where the liner has filled in scratches, recesses and other topological imperfections on the wafer, the liner material must be removed at the expense of removing the surrounding wafer material. As such, a considerable amount of intermetal dielectric (IMD), which is coplanar with the damascene interconnect or via surface, is removed while removing all the liner material from the lowest portions of the topological imperfections.
Typical IMD removals range from 50-100 nm for thin (about 100-300 nm height) single damascene wire level to 100-250 nm for a super thick (about 3 um height) wire. Accordingly, the IMD erosion during the CMP process requires the wires or vias to be fabricated with pre-metallization heights greater than the final metallization heights, which increases the chance of unwanted voids or inclusions being formed in the wire or via.
Wire height and aspect ratio for interconnects formed during a damascene process using a post reactive ion etch (RIE) and a post CMP material removal process are shown in Table A. Each row in Table A corresponds to a particular type of device upon which the damascene interconnect formation process was used. As can be seen from Table A, a damascene process for a 90 nm generation M1 has a wire height of 280 nm with an aspect ratio of 2.50 after the RIE etch, and a wire height of 180 nm with an aspect ratio of 1.61 after the CMP step. Accordingly, about 100 nm of material has been eroded from the interconnect structure during the CMP step. For a relatively large wire such as 130 nm generation 6X wire, the post RIE wire height is 3.3 um with an aspect ratio of 2.8, and the post CMP wire height is 3.0 um with an aspect ratio of 2.5.
TABLE APost RIEAspectPost CMPAspectWire HeightsRatioWire HeightsRatio90 nm280nm2.50180 nm1.61generation M190 nm380 nm2.71250nm1.79generation M390 nm550nm1.96400nm1.43generation 2XWire130 nm3.3um2.8 3.0um2.5 generation 6XWire
Accordingly, as the trend shown in Table A indicates, the amount of material eroded during the CMP step remains relatively constant regardless of the size of the wire being formed by the damascene process. Consequently, as wire size shrinks, a larger proportion of wire will be eroded during the CMP step, thus requiring ever increasing aspect ratios and a corresponding increase in the chance of a void or inclusion formation during the damascene process. As such, wire erosion during the damascene process will have an increasingly negative impact on fabrication yield for smaller and smaller interconnects and devices. Although the damascene process typically uses a conductor as trench-fill material, a non-conductor may also be used as trench-fill material.